1. Field of the Invention
The invention relates to the design of electronic circuits and more particularly to optimized mapping of cells having different threshold voltages to an integrated circuit design.
2. Description of the Related Art
Synthesis of an integrated circuit design involves a process of translation of a behavioral description of the design to a structural description of the design optimized according to one or more constraints such as timing, power dissipation, area or testability. A designer ordinarily sets forth a behavioral description of a design in a high level descriptive language (HDL) such as Verilog or VHDL, or describes a model of the design in the C or C++ programming language, for example. Ordinarily, an HDL description describes a register transfer level (RTL) model of a design in terms of data flow between registers that store information between clock cycles in a circuit.
In an RTL description storage devices (i.e., registers) store current circuit state information, and a set of logical equations define the next state of the circuit. The next circuit state is stored in the storage devices in response to a clock signal defined for the circuit. The clock signal defines the interval of time in which the next state is to be computed, and is used by the storage devices to determine when to sample an input to the storage device. An input value thus sampled is stored in the storage device until the subsequent sampling point occurs upon the occurrence of a later clock signal.
During synthesis, an RTL behavioral description of a circuit design is converted into a netlist, which is a list of electronic logic cells with a description of the interconnections between inputs and outputs of the various cell instances. The cells of the netlist are used to implement the logical next state equations of the RTL description. The cells in the netlist are obtained from of a cell library. A cell represents a circuit element that is available in a particular implementation technology. A cell library may comprise a few hundred cells corresponding to primitive function circuits, such as inverters, NAND gates, NOR gates and possibly to more complex Boolean function circuits and perhaps, to sequential elements like latches and flip-flops.
A cell may itself be defined in terms of a netlist that includes a cell model that specifies logical, electrical, and physical attributes and that may include one or more primitives circuits. One typical cell attribute is its logical function (e.g., AND, OR, NAND, NOR, INVERT, etc., or a complex logical function implementing an equation of basic combinational or sequential functions). Other cell attributes provide information concerning a variety of the cell's characteristics such as timing, area, power dissipation, testability and threshold voltage (Vt), for example.
During synthesis, cells are mapped from the cell library to a netlist generated from the RTL description. A typical cell library may include multiple cells that have the same basic function attribute but differ in one or more other attributes. For example, a cell library may include multiple different cells that perform a two-input NAND logic function, but each such functionally equivalent cell may employ transistors having different threshold voltages (Vt).
Synthesis uses constraint-driven optimization techniques to select from among multiple cells with similar functionalities when mapping cells to netlist locations. Optimized mapping based upon cell threshold voltage has become increasingly important since the impact of leakage power upon performance increases as the physical dimensions of circuit become smaller. In general, a lower Vt transistor can switch (i.e., change states) more rapidly than a higher Vt transistor. A lower Vt transistor typically has a larger leakage current than a higher Vt transistor. As a result, a lower Vt transistor ordinarily dissipates more power than a higher Vt transistor. Thus, there often is an inherent trade-off between power dissipation and switching speed when selecting between cells having different threshold voltages.
In particular, transistor sub-threshold leakage current grows exponentially and becomes an increasingly large component of total power dissipation with scaling down of technology. For instance, the drain current of a MOSFET in the sub-threshold region can be expressed as (assuming Vds [drain to source voltage] is large compared to the thermal voltage)(1) Ithreshold=I0+10((Vgs-Vt)/S)  (1)where, I0 is the drain current with Vgs [gate to source voltage]=Vt [threshold voltage] and S is the sub-threshold slope. It will be appreciated that even a small decrease in Vt can result in an order of magnitude increase in the sub-threshold leakage current.
Consequently, multiple-Vt optimization aimed at leakage power optimization has become an important phase of synthesis. During a multiple-Vt optimization phase, cells are mapped to netlist locations based at least in part upon threshold voltage constraints. Typically, lower Vt cells are selected for timing critical circuit paths, and higher Vt cells are selected for non-critical timing paths to reduce leakage current.
Unfortunately, there have been shortcomings with prior multiple Vt optimization techniques. Past approaches to multiple-Vt optimization often involved name-based cell identification that placed a heavy reliance on library cell names to identify cells having similar functionality but different threshold voltages. In other words, these prior techniques often relied upon a library vendor having named cells with sufficient clarity to discern cells having different threshold voltages but the same functionality. For example, in order to satisfy timing constraints, an optimization process might seek to replace a high Vt cell with a functionally equivalent low Vt cell. Under an earlier approach, identification of the corresponding low Vt cell would be largely dependent on matching the name of the low Vt cell with a name of the high Vt cell in the library. For instance, functionally equivalent cells may be named ANDHVT20 and ANDLVT20, where H stands for high-vt and L stands for low-vt so as to form a basis for name-based cell replacement. This name based approach has other potential drawbacks. For example, it may be unclear what Vt-based selection criteria to use if a corresponding low Vt cell or high Vt cell counterpart to a given cell does not exist in the library. The name based mapping process also places a heavy reliance upon correct designation of cell names in vendor libraries. Occasionally, an HVT cell may be incorrectly designated as an LVT cell in a vendor library, which can lead to degradation of overall results in terms of power.
Moreover, prior synthesis flows often comprised an initial optimization using low Vt cells followed by leakage reclamation using high Vt cells. Unfortunately, this synthesis flow has drawbacks. For example, leakage power obtained with this prior flow may not be optimal since the initial passes did not use high Vt cells for optimization.
Thus, there has been a need for improvement in the selection and use of cells for multiple threshold voltage optimizations during synthesis. The present invention meets this need.